(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of pattern loading on a photolithographic exposure mask such that effects of different etching bias while applying the same dry-etching parameters are eliminated.
(2) Description of the Prior Art
For the creation of semiconductor devices a large number of interactive device elements are created in or over the surface of a substrate.
After a layer of semiconductor material, such as a layer of dielectric or a layer of insulating material, has been deposited over a substrate, this layer has to be patterned and etched in order to selectively remove the layer and in so doing to create a desired pattern in the remaining layer of semiconductor material.
For this purpose, the layer is typically coated with a layer of photoresist, which is exposed through a photolithographic exposure mask over the surface of which a positive or negative image of the desired pattern has been created. In this manner, the created photoresist mask exposes the surface of the underlying layer that must be removed and blocks the underlying layer where this layer is to remain in place. The underlying layer may for instance be a layer of metal such as aluminum, copper, tungsten or any semiconductor material that is typically used for the creation of device elements or for the creation of interconnecting elements thereof.
The removal of the material that is exposed by the photoresist mask is typically performed by applying an etch of the exposed underlying material. This etch is determined by a number of etch parameters such as etchant used, the flow rate of the etchant, the temperature and pressure applied during the etch and, not insignificantly, the time of the etch.
It is clear that the longer the etch is applied the more of the exposed underlying material will be removed. It is thereby well known in the art that the etch removal rate of the underlying material depends on the pattern density of the material that needs to be removed, whereby smaller pattern features require a larger etch time for removal of the etched layer than larger pattern features etched in the underlying layer. This latter effect is known in the art as the loading effect, whereby it is clear that this loading effect can lead to serious problems of uneven etch removal rates over the surfaces of a substrate.
One of the methods that are used to counter the loading effect is to extend etch time so that smaller feature size material can be removed in this extended etch time. This however presents the problem of photoresist punchthrough, undesirably exposing parts of the underlying layer and etching the layer outside the boundaries of the desired pattern.
In addition, the non-uniform removal of etched layers may affect deposition rates of subsequently there-over deposited layers of semiconductor material. For instance, the deposition of a layer of passivation material over the surface of a patterned and etched layer of metal is inversely proportional to the thickness of the layer of metal over which the layer of passivation is deposited.
The negative impact of the above indicated loading effect becomes even more of a challenge for applications where different types of devices area are created over one substrate. For these applications, feature and device densities vary in an even more pronounced manner over the surface of the substrate in view of the different topography that is in existence during the processing of the substrate.
It is therefore desirable to have a method that allows for the creation of semiconductor devices and device features having different densities by applying one process recipe that is equally applicable to these semiconductor devices and device features.
U.S. Pat. No. 6,281,049 B1 (Lee) shows a mask process with dummy patterns involving macro loading.
U.S. Pat. No. 5,899,706 (Kluwe et al.) shows a process to reduce loading variation during etching.
U.S. Pat. No. 5,278,105 (Eden et al.) shows a method for a device with dummy lines in active layers.